The invention relates to a method of applying alignment marks to a semiconductor wafer.
U.S. Pat. No. 5,786,260 discloses a method of applying alignment marks to a semiconductor wafer in which depressions are formed in a surface region of the semiconductor wafer, lands being formed between the depressions, an intermediate layer then being applied and then an insulating layer or else a metal layer. During a subsequent CMP process, the insulating layer or the metal layer is removed, by using the dishing behavior, in such a way that the edges of the alignment marks are exposed and stand out. A subsequent etching step for the remaining removal of the insulating layer or metal layer in the depressions is specified as optional.
U.S. Pat. No. 6,051,496 discloses the use of a stop layer during the CMP process, said layer being deposited on a dielectric layer having lands and depressions, specifically in particular in the case of a CU damascene.
U.S. Pat. No. 6,080,636 discloses a production process for a photolithographic alignment mark by means of a CMP process.
U.S. Pat. No. 6,020,263 discloses a method of exposing alignment marks following a CMP process on tungsten metal.
The structuring of semiconductor wafers in order to produce microelectric components is carried out almost entirely nowadays with the aid of lithographic techniques. In this case, the structures are initially produced via a photo mask in a thin radiation-sensitive resist layer, normally an organic photoresist layer, which is applied to the semiconductor wafer. By means of a suitable developer, the irradiated or unirradiated regions are then removed. The resist pattern produced in this way is used as a mask for a subsequent process step, for example etching or ion implantation, with which the pattern is transferred into the semiconductor structure layer lying underneath. The resist mask is then dissolved away again.
In this case, for the quality of the lithographic method it is critical to transfer the resist structure in correct position to the semiconductor layer lying underneath. In this case, it is in particular necessary to align the exposure device accurately in relation to the semiconductor wafer in order to form the mask structure. In order to align the exposure device, therefore, alignment marks are generally applied to the semiconductor wafer. These alignment marks are generally a structure comprising bars and lines which, in general, are executed in the kerf region of the semiconductor wafer. The kerf region of the semiconductor wafer represents a region about 50 to 100 xcexcm wide between the individual chips on the semiconductor wafer which, when the semiconductor wafer is subsequently broken up into the individual chips, is then destroyed. However, the alignment operation is difficult when an additional, optically non transparent layer is applied, which is needed for example for the production of a capacitor, and therefore the alignment mark structure lying underneath in the semiconductor wafer cannot be registered optically. In such a case, the application of the alignment marks to the semiconductor wafer in the prior art is then carried out in such a way that, during the etching of the preceding structure into the semiconductor wafer, at the same time the bars and lines are etched into the kerf area, the alignment masks being designed in such a way that during the following process steps, including the deposition of the optically non transparent layer, said alignment marks are no longer completely filled. The topology of the alignment marks on the semiconductor wafer can then be registered by means of optical alignment mark detection methods and can be used to align the exposure device.
However, this manner of forming the alignment marks proves to be unsuitable in particular when it is intended to be carried out in the context of the damascene technique, which is used substantially for structuring a metallization plane. In the damascene technique, which is primarily used for structuring copper, in order to produce the metal wiring, at the location of the conductor tracks depressions are etched into the oxide lying underneath. In this etching step, the alignment mark structure is then also formed in accordance with the conventional method. There then follows the sputtering on or deposition of a thin start layer to form a nucleus for the subsequent metal deposition over the entire area. By means of chemical-mechanical polishing of the metal layer down as far as the surface of the etched trenches, the desired conductor tracks are then produced. Since, in the damascene method, substantially perfect planarization of the metal layer is carried out, the topology of the alignment marks is also largely leveled during the chemical-mechanical polishing, so that said alignment marks no longer stand out following the application of a following, optically non transparent layer. Furthermore, in particular in the copper damascene method, the trenches etched for the alignment marks also cannot be formed in such a way that these are not filled up completely during the copper deposition, since copper always begins to fill all the trenches from the bottom up, irrespective of their width, during the deposition methods which are normally used, and it is therefore not possible either to produce any voids, that is to say cavities, in the trenches, which then lead to a topology of the alignment marks on an optically non transparent layer that is subsequently deposited.
In order to solve this problem, therefore, also in the prior art, in particular in the damascene method, a topology of the alignment marks is produced by means of a further lithographic and etching step, which itself requires only inaccurate alignment. For this purpose, following the production of the alignment marks, and the subsequent deposition of the optically non transparent layer, the alignment mark structure is transferred via a dedicated photo mask to a thin radiation-sensitive layer which is applied to the optically non transparent layer. The alignment marks are then exposed by a subsequent etching step. However, this additional lithographic and etching step is complicated and expensive.
It is therefore an object of the present invention to provide a simple and cost-effective method of applying alignment marks to a semiconductor wafer which may be used in particular in conjunction with structuring of the semiconductor wafer with the aid of the damascene technique.
According to the invention, to apply alignment marks, an intricate structure consisting of a non metal is produced in a large-area metal layer on at least one area of a semiconductor wafer. This area of the semiconductor wafer having the large-area metal layer is then planarized by means of chemical-mechanical polishing, the non metal structure in the metal layer and the chemical-mechanical polishing process being coordinated with each other in such a way that the non metal structure stands out from the large-area metal layer.
Forming the alignment marks in accordance with the invention follows the model of the damascene technique, but as opposed to the conventional alignment mark design, a structure consisting of a non metal is produced in a large-area metal layer. This design makes it possible to make specific use of two effects generally viewed as negative during planarization with the aid of the chemical-mechanical polishing.
This is because, during chemical-mechanical polishing, large-area metal surfaces, if they are to be leveled, tend to be removed to too great an extent, that is to say tend to a dishing behavior. Then, in the structure according to the invention, this leads to the intricate non metal structure present in the metal layer standing out, so that a topology that can be used as alignment marks is produced on a non transparent layer which is subsequently applied.
Furthermore, in order to make the alignment marks contrasty, use can also be made of the effect that occurs during chemical-mechanical polishing, that intricate non metal structures in a large-area metal layer, if the latter is to be planarized, likewise tend to be removed to too great an extent as compared with the surrounding metal layer, that is to say tend to erode, and therefore to form trenches in the metal layer. This trench formation of the alignment marks then ensures a topology on the non transparent layer which is subsequently applied, which is suitable for aligning an exposure device.
Depending on the design of the chemical-mechanical polishing operation and the design of the metal surface and the non metal structure contained therein, it is therefore possible to cause the non metal structure to stand out owing to a dishing behavior of the metal surface or this non metal structure to form trenches in the metal surface owing to an erosion behavior, which is then reflected in a topology on the non transparent layer arranged above it.
According to a preferred embodiment, the application of the alignment mask is carried out in the damascene technique, the large-area metal layer being deposited onto a layer consisting of a dielectric and having large-area depressions. In this case, between the dielectric layer and the metal layer, the further thin intermediate layer is provided in order to form a nucleus for the metal deposition and as a diffusion barrier.
The chemical-mechanical polishing process is carried out in two stages, the metal layer being removed in a first stage and being stopped on the intermediate layer lying underneath. During this first polishing step, dishing takes place in the large metal surfaces between the projecting dielectric structures, the intermediate layer on the projecting dielectric structures also partly being removed. In a second polishing step, the intermediate layer on these projecting dielectric structures is then removed, the polishing operation being stopped in the dielectric. During this second polishing operation, intensive overpolishing of the intermediate layer, and therefore erosion of the dielectric layer lying underneath, take place, so that trenches form between the large-area metal layers and then still remain detectable as alignment marks following the application of a non transparent layer.
This method sequence makes it possible, in particular when copper is used as the metal layer and tantalum/tantalum nitride as the intermediate layer, to use the formation of alignment marks also within the context of copper metallization in order to form conductor tracks.
The invention will be explained in more detail using the appended drawings, in which: